Correlation detector and communication apparatus

ABSTRACT

A correlation detector is provided which can establish initial acquisition quickly, and achieve high accuracy tracking by extracting crosscorrelation components in a receiver for CDMA communication, and a communication system using the correlation detector is also provided. During the initial acquisition, a received signal 21 is supplied to a matched filter 43. When an acquisition decision circuit 45 decides that the matched filter 43 detects the acquisition, it controls a switching circuit 42 to supply the received signal 21 to multipliers 47 and 48, and resets a VCCG 29 and a spreading code replica generator 30. After establishing the acquisition, a received spreading code is quasicoherent detected, and the detected spread signal is multiplied by a phase advanced replica and a phase retarded replica. Correlation detection signals are produced from the products, and squared components of the correlation detected signals are generated, summed in the opposite phase, and averaged along the time axis. The averaged signal is inversely modulated by a decision signal of received data to obtain a phase error signal, the decision signal being obtained by multiplying the received spread signal by a replica in synchronism with the received spread sinal, and by integrating the product over a plurality of chips to compensate for a receive phase error. The replica generator is driven by a clock signal whose phase is controlled by the phase error signal.

TECHNICAL FIELD

The present invention relates to a correlation detector of a radioreceiver in a CDMA (Code Division Multiple Access) system which carriesout multiple access by using a spread spectrum in mobile communications.

In particular, the present invention relates to a CDMA synchronizingcircuit that synchronizes a spreading code for despreading the receivedsignal to a spreading code in a received signal in CDMA communications.

BACKGROUND ART

CDMA communications perform multiple access propagation by spreadinginformation into wideband signals using spreading codes with rateshigher than the rate of the information, and are roughly divided intodirect sequence (DS) systems that spread modulated signals by high ratespreading codes, and frequency hopping (FH) systems. The FH systemresolves each symbol into smaller elements called chips, and translatesthe chips into signals with different center frequency at a high speed.Since the implementation of the FH system is difficult, the DS system isgenerally used. The DS system recovers the original narrowband signal bydespreading the wideband received input signal at a receiving end,followed by demodulation. In the despreading process, correlationdetection is performed between the spreading code included in thereceived signal and a spreading code generated at the receiving end.

Thus, the receiver for receiving the spread signal in the DS system isusually provided with a replica (reference PN sequence) of the PNsequence (received PN sequence) in the received signal, and establishessynchronization between the reference PN sequence and the received PNsequence. FIG. 1 shows a conventional synchronization circuit using amatched filter. The received signal applied to an input terminal 10 issupplied to a memory circuit 11 with taps. The number of taps of thetapped memory circuit 11 is the same as the number of chips in aspreading code interval (that is, a processing gain PG). The outputs ofthe taps of the memory circuit 11 are multiplied by the referencespreading code stored in a tap coefficient circuit 13 by multipliers 12.The resultant products are summed by an integrator 14, which outputs thesum from its output terminal 16 as a correlation value 15.

Using the matched filter makes it possible to quickly establish thesynchronization because the peaks of the correlation value appear at thesame interval as that of the spreading code. However, since the capacityof the tapped memory circuit 11 and the number of the multipliers 12increase in proportion to the processing gain, the power consumption ofthe receiver will increase with the interval of the spreading code.Therefore, the conventional synchronizing circuit is not appropriate forportable devices or mobile devices.

Using a sliding correlation detector as shown in FIG. 2 makes possiblepower saving and downsizing of the circuit. In FIG. 2, a received signal21 inputted to the input terminal 10 is multiplied by a spreading code,which is generated by a spreading code replica generator 30, by amultiplier 22 to obtain the correlation between the two. The resultantproduct is passed through a bandpass filter (BPF) 23, followed by peakpower detection by a square-law detector 24. The detected power isintegrated over a fixed time (normally, ± one chip interval) by anintegral-dump circuit 25. The integrated result is compared with athreshold value by a threshold value decision circuit 26 which decidesthat initial acquisition has been completed if the integrated resultexceeds the threshold value, and proceeds to the next step (trackingmode). If the integrated result is less than the threshold value, thedecision circuit 26 supplies a control voltage 28 to a voltagecontrolled clock generator (VCCG) 29 which slides the phase of thereplica so that the phase of the spreading code generated by thespreading code replica generator 30 is shifted by 1/N chip interval (Nis a natural number equal to or greater than one). The initialacquisition has been completed by repeating the processing until thesynchronized point is found.

According to this method, it is necessary to integrate the spreadingreplica over the fixed time every time the replica is shifted by 1/Nchip interval, and to detect the synchronized point in the interval ofthe spreading code by comparing the integrated result. This willlengthen the acquisition time, and hence, it is not appropriate for asystem which requires a quick acquisition.

In addition, the conventional correlation detector presents anotherproblem in that it provides a rather large error in maintaining(tracking) the synchronization.

FIG. 3 is a block diagram showing a conventional DLL (Delay Locked Loop)correlation detector 44. In FIG. 3, the same functional blocks aredesignated by the same numerals as in FIG. 2. The reference numeral 10designates a spreaded signal input terminal, 102 designates a decideddata output terminal, 111 denotes a multiplier, and 510 designates adelay circuit. The correlation detector 44 calculates correlationsbetween the input modulated signal and code sequences formed byadvancing and retarding the chip phase of the replica by 1/N,respectively. The correlated signals are passed through bandpass filters(BPFs) 53 and 54 which eliminate unnecessary high frequency components,and are detected by square-law detectors 55 and 56. The squaredamplitude components are summed by an adder 57 in the opposite phase, sothat an error signal voltage is obtained which indicates an amount of aphase difference. The error signal voltage is passed through a loopfilter 58, and is fed back to a VCCG 29 to correct the phase of thereplica code sequence. The phase advance (or retardation) time δ rangesfrom 0 to Tc, where Tc is the chip interval.

Applying the CDMA system to cellular communications requires highaccuracy transmission power control that keeps constant base station'sreceived levels of signals sent from all the mobile stations. The CDMAsystem can increase the capacity in terms of the number of subscribersper frequency band as compared with the FDMA system or the TDMA system.This is because conventional systems which employ frequencyorthogonality cannot utilize the same carrier frequencies in thecontiguous cells, and even space diversity systems cannot reuse the samefrequencies within four cells.

In contrast with this, the CDMA system makes it possible to reuse thesame carrier frequency in the contiguous cells because the signals ofthe other communicators are regarded as white noise. Accordingly, theCDMA system can increase the capacity in terms of the number ofsubscribers as compared with the FDMA system or the TDMA system. If theprocessing gain is pg, the number of spreading code sequences thatcompletely orthogonalize with each other is pg. This number of the codesequences, however, will be insufficient when information data is spreadby using only code sequences of one symbol interval long. To overcomethis problem, the number of the spreading codes is increased almostinfinitely by superimposing long code sequences of a very long intervalover short code sequences of one symbol interval.

Unlike M sequences that have definite autocorrelation characteristics,the autocorrelation of Gold sequences and that of the sequences obtainedby superimposing very long code sequences over the Gold sequences willhave undesired peaks of considerable amplitudes in addition to thenormal correlation peak in one symbol interval. As a result, when thereceived signal level is low, a lock may be lost in the conventionaldelay-locked loop using one chip interval lock. Let us formulate theoperation principle of the delay-locked loop of FIG. 3. First, the inputsignal is expressed by the following equation. ##EQU1## where S isaverage signal power, c(t-τ_(t)) is a received spreading code includinga propagation delay, m(t-τ_(t)) represents data modulation including thepropagation delay, ω₀ is the angular frequency of a carrier, and Ω(t)=Ω₀+Θ_(0t) is an unknown carrier phase which is represented as the sum of aconstant term and a term proportional to the Doppler frequency. Thepower spectrum density of n(t) is N_(0/2). δω₀ is an angular frequencyerror between the center frequency of a modulation signal and a localoscillation frequency. In addition, the bandpassed expression of inputthermal noise ni(t) is given by ##EQU2## where N_(c) (t) and N_(s) (t)are assumed to be approximately and statistically independent andsteady. The spreading replica sequence of the advanced phase and that ofthe retarded phase can be expressed as follows:

    C(t-τ.sub.t +δ),C(t-τ.sub.t -δ)        (2A)

where τ_(t) is a propagation delay estimated by the DLL at the receivingside. The crosscorrelation output of the phase detector is expressed as##EQU3## where K_(m) is the gain of the phase detector which is assumedto be equal in both branches, and X represents the average of a set.

FIGS. 4A-4B illustrate the autocorrelation outputs in terms of thereceived chip phase error. Here,

    ε.sub.t ≡(τ.sub.t -τ.sub.t)/Tc       (3A)

is a normalized propagation delay error. H(s) is a lowpass expression ofa transfer function H(s) of the bandpass filter, and

    ε.sub.t± (t-τ.sub.t ε.sub.t)≡c(t-τ.sub.t)c(t-τ±δ)-c(t-τ.sub.t)c(t-τ.sub.t ±δ)                            (4)

is a process of a PN sequence.

The output of the square-law detector can be expressed as follows usingR_(pN)± (x) which is a function obtained by shifting the autocorrelationfunction of PN by a time period of +x. ##EQU4## where

    m(t)=H.sub.ι (P)m(t)

    ε.sub.c± (t,ε.sub.t)=H.sub.ι (P)[m(t)ε.sub.c± (t,ε.sub.t)]

    N.sub.c± (t)=H.sub.ι (P)[m(t)c(t-τ.sub.t ±ε.sub.t)N.sub.c (t)]

    N.sub.s± (t)=H.sub.ι (P)[m(t)c(t-τ.sub.t ±ε.sub.t)N.sub.s (t)]                          (6)

Here, H/(p)×(t) expresses an output response of the BPF to x(t). If thebandwidth B_(L) is sufficiently smaller than the chip rate, the effectof the auto-noise caused by the PN sequence on the loop is negligible inthe first-order approximation. Neglecting the auto-noise and thesecondary harmonic caused by the square-law detection, the input to theloop filter can be expressed by the following equation.

    e(t)≡y.sub.-.sup.2 (t)-y.sub.+.sup.2 (t)=SK.sub.m.sup.2 m.sup.2 (t-τ.sub.t)D(ε.sub.t)+K.sub.m.sup.2 n.sub.e (t,ε.sub.t)(7)

where

    D(ε.sub.t)≡R.sup.2 PN-(ε.sub.t)-R.sup.2 PN+.sup.2 (ε.sub.t)                                         (7A)

According to the foregoing, a normalized delay estimate of the output ofthe spreading code replica generator is expressed by the followingequation using e(t). ##EQU5## where F(s) is the transfer function of theloop filter, and K_(VCC) is the gain of a voltage controller in the VCCGwhich drives the PN sequence generator. Placing K=Km² K_(VCC), Krepresents the loop gain. Substituting equation (7) into (8), ##EQU6##Thus, estimated error ε_(t) is expressed as ##EQU7## Resolving the firstterm in the blanket of the above equation into an average value term andmodulated auto-noise term gives ##EQU8## where < > expresses an averagein time, and ##EQU9## where Sm(f) is a power spectrum density of thedata modulation. The M₂ term is the integral of the data modulationpower spectrum density over the passband of the filter, and indicatesthe data modulation power in the passband. Since the bandwidth of theloop is much smaller than the data symbol rate, the auto-noiseassociated with the second term of equation (11) is negligible.

From equation (10), the following equation is obtained. ##EQU10## wherea dot placed over characters represents a time differential, and η isgiven by ##EQU11##

Briefly, the average of squared tracking jitter due to noise componentis expressed as follows: ##EQU12## where B_(L) is an equivalent noisebandwidth of the LPF, and N_(e) (ε_(t)) is expressed as ##EQU13## wheref(ε_(t)) represents a square-law detection curve.

Since the conventional DLL uses the square-law detector as shown inequation (15), the noise component is also squared. This will increasethe tracking jitter as shown in equation (14).

DISCLOSURE OF THE INVENTION

Therefore, an object of the present invention is to provide a lowpower-consumption CDMA synchronizing circuit capable of high speedsynchronization. Another object of the present invention is to provide acorrelation detector that can perform high accuracy tracking capable ofeliminating the square loss resulting from the emphasis of the noisecomponent by the square-law detector, which differs from theconventional code tracking circuit.

In a first aspect of the present invention, there is provided asynchronizing apparatus including a tracking means for maintainingsynchronization between a received signal and a despreading code byusing a correlation between the received signal and the despreadingcode, the received signal being CDMA spread and received by a receiver,and the despreading code being used for despreading the received signal,the tracking means comprising:

replica generating means for generating a phase advanced replica of aCDMA spreading code with an advance phase with respect to the receivedsignal, and a phase retarded replica of the CDMA spreading code with aretarded phase with respect to the received signal;

first multiplication means for multiplying the received signal by thephase advanced replica;

second multiplication means for multiplying the received signal by thephase retarded replica;

a first filter for extracting from an output signal of the firstmultiplication means a first correlation detection signal indicating acorrelation between the phase advanced replica and the received signal;and

a second filter for extracting from an output signal of the secondmultiplication means a second correlation detection signal indicating acorrelation between the phase retarded replica and the received signal.

The tracking means may further comprise compensation means forcompensating for the correlation detection signals on the basis of adespreading code generated by despreading the received signal.

The replica generating means may further comprise means for generating areplica of the CDMA spreading code whose phase is in synchronism withthe received signal; and the tracking means comprises:

carrier frequency error compensation means for compensating for acarrier frequency error associated with the first and second correlationdetection signals;

addition means for summing in opposite phase the first and secondcorrelation detection signals, which have been compensated by thecarrier frequency error compensation means;

averaging means for averaging an output signal of the addition meansalong a time axis;

multiplication means for multiplying the received signal by the replicain synchronism with the received signal;

integral means for integrating an output signal of the multiplicationmeans over M chip intervals;

automatic frequency control means for detecting the carrier frequencyerror from an output signal of the integral means, and for compensatingfor the carrier frequency error;

decision means for outputting a decided signal of received data byperforming received phase error compensation on the output signal of theintegral means;

inverse modulation means for inversely modulating an output signal ofthe averaging means by the decided signal; and

clock generating means for outputting a clock signal whose phase iscontrolled by a phase error signal outputted from the inverse modulationmeans,

wherein the replica generating means generates the replica in accordancewith the clock signal generated by the clock generating means.

The synchronizing apparatus may further comprise:

initial acquisition means including tapped storing means for storing thereceived signal of at least one spreading code interval long, tapcoefficient means for storing the despreading code, fourthmultiplication means for multiplying individual chips stored in thetapped storing means by stored patterns of the despreading code storedin the tap coefficient means, and second addition means for summingoutputs of the fourth multiplication means; and

switching means for supplying the received signal to the initialacquisition means when a phase difference between the received signaland the despreading code is greater than a predetermined value, and forsupplying the received signal to the tracking means when the phasedifference is smaller than the predetermined value.

In a second aspect of the present invention, there is provided a CDMAcommunication apparatus including a tracking means for maintainingsynchronization between a received signal and a despreading code byusing a correlation between the received signal and the despreadingcode, the received signal being CDMA spread and received by a receiver,and the despreading code being used for despreading the received signal,the tracking means comprising:

replica generating means for generating a phase advanced replica of aCDMA spreading code with an advance phase with respect to the receivedsignal, and a phase retarded replica of the CDMA spreading code with aretarded phase with respect to the received signal;

first multiplication means for multiplying the received signal by thephase advanced replica;

second multiplication means for multiplying the received signal by thephase retarded replica;

a first filter for extracting from an output signal of the firstmultiplication means a correlation detection signal indicating acorrelation between the phase advanced replica and the received signal;and

a second filter for extracting from an output signal of the secondmultiplication means a correlation detection signal indicating acorrelation between the phase retarded replica and the received signal.

The tracking means may further comprise compensation means forcompensating for the correlation detection signals on the basis of adespreading code generated by despreading the received signal.

The replica generating means may further comprise means for generating areplica of a CDMA spreading code, whose phase is in synchronism with thereceived signal; and the tracking means comprises:

third multiplication means for multiplying the received signal by thereplica in synchronism with the received signal;

integral means for integrating an output signal of the thirdmultiplication means over M chip intervals;

automatic frequency control means for detecting a carrier frequencyerror from an output signal of the integral means, and for compensatingfor the carrier frequency error;

carrier frequency error compensation means for compensating for thecarrier frequency error associated with outputs of the first and secondcorrelation detection signals;

addition means for summing in opposite phase the output of the firstfilter and the output of the second filter, which have been compensatedby the carrier frequency error compensation means;

averaging means for averaging an output signal of the addition meansalong a time axis;

decision means for outputting a decided signal of received data byperforming received phase error compensation on the output signal of theintegral means;

inverse modulation means for inversely modulating an output signal ofthe averaging means by the decided signal; and

clock generating means for outputting a clock signal whose phase iscontrolled by a phase error signal outputted from the inverse modulationmeans,

wherein the replica generating means is driven by the clock signalgenerated by the clock generating means.

The CDMA communication apparatus may further comprise:

initial acquisition means including tapped storing means for storing thereceived signal of at least one spreading code interval long, tapcoefficient means for storing the despreading code, fourthmultiplication means for multiplying individual chips stored in thetapped storing means by stored patterns of the despreading code storedin the tap coefficient means, and second addition means for summingoutputs of the fourth multiplication means; and

switching means for supplying the received signal to the initialacquisition means when a phase difference between the received signaland the despreading code is greater than a predetermined value, and forsupplying the received signal to the tracking means when the phasedifference is smaller than the predetermined value.

In a third aspect of the present invention, there is provided asynchronizing method including a tracking step of maintainingsynchronization between a received signal and a despreading code byusing a correlation between the received signal and the despreadingcode, the received signal being CDMA spread and received by a receiver,and the despreading code being used for despreading the received signal,the tracking step comprising the steps of:

generating a phase advanced replica of a CDMA spreading code with anadvance phase with respect to the received signal, and a phase retardedreplica of the CDMA spreading code with a retarded phase with respect tothe received signal;

multiplying the received signal by the phase advanced replica;

multiplying the received signal by the phase retarded replica; and

extracting, from products of the multiplications, correlation detectionsignals indicating correlations between the replicas and the receivedsignal.

The tracking step may further comprise a step of compensating for thecorrelation detection signals on the basis of a despreading codegenerated by despreading the received signal.

The synchronizing method may further comprise a step of generating areplica of the CDMA spreading code whose phase is in synchronism withthe received signal, and wherein the tracking step comprises:

compensating for a carrier frequency error associated with the twocorrelation detection signals;

addition means for summing in opposite phase the two correlationdetection signals whose carrier frequency error is compensated;

averaging a summed result along a time axis;

multiplying the received signal by the replica in synchronism with thereceived signal;

integrating the product over M chip intervals;

detecting the carrier frequency error from the integrated signal, andfor compensating for the carrier frequency error;

outputting a decided signal of received data by performing receivedphase error compensation on the integrated signal;

inversely modulating the averaged summed result by the decided signal,thereby generating a phase error signal; and

generating a clock signal whose phase is controlled by the phase errorsignal,

wherein the replica is generated in accordance with the clock signal.

The synchronizing method may further comprise:

an initial acquisition step of storing the despread code, storing thereceived signal of at least one spreading code interval long,multiplying individual chips of the received signal by individualpatterns of the despreading code, and summing the products; and

switching step of performing initial acquisition of the received signalin the initial acquisition step when a phase difference between thereceived signal and the despreading code is greater than a predeterminedvalue, and of tracking the received signal in the tracking step when thephase difference is smaller than the predetermined value.

In a fourth aspect of the present invention, there is provided a CDMAcommunication system including receivers, each of the receivers beingprovided with a tracking means for maintaining synchronization between areceived signal and a despreading code by using a correlation betweenthe received signal and the despreading code, the received signal beingCDMA spread and received by the receiver, and the despreading code beingused for despreading the received signal, the tracking means comprising:

replica generating means for generating a phase advanced replica of aCDMA spreading code with an advance phase with respect to the receivedsignal, and a phase retarded replica of the CDMA spreading code with aretarded phase with respect to the received signal;

first multiplication means for multiplying the received signal by thephase advanced replica;

second multiplication means for multiplying the received signal by thephase retarded replica;

a first filter for extracting from an output signal of the firstmultiplication means a correlation detection signal indicating acorrelation between the phase advanced replica and the received signal;and

a second filter for extracting from an output signal of the secondmultiplication means a correlation detection signal indicating acorrelation between the phase retarded replica and the received signal.

The tracking means may further comprise compensation means forcompensating for the correlation detection signals on the basis of adespreading code generated by despreading the received signal.

The replica generating means may further comprise means for generating areplica of a CDMA spreading code, whose phase is in synchronism with thereceived signal; and the tracking means comprises:

third multiplication means for multiplying the received signal by thereplica in synchronism with the received signal;

integral means for integrating an output signal of the thirdmultiplication means over M chip intervals;

automatic frequency control means for detecting a carrier frequencyerror from an output signal of the integral means, and for compensatingfor the carrier frequency error;

carrier frequency error compensation means for compensating for thecarrier frequency error associated with outputs of the first and secondcorrelation detection signals;

addition means for summing in opposite phase the output of the firstfilter and the output of the second filter, which have been compensatedby the carrier frequency error compensation means;

averaging means for averaging an output signal of the addition meansalong a time axis;

decision means for outputting a decided signal of received data byperforming received phase error compensation on the output signal of theintegral means;

inverse modulation means for inversely modulating an output signal ofthe averaging means by the decided signal; and

clock generating means for outputting a clock signal whose phase iscontrolled by a phase error signal outputted from the inverse modulationmeans,

wherein the replica generating means is driven by the clock signalgenerated by the clock generating means.

The CDMA communication system may further comprise:

initial acquisition means including tapped storing means for storing thereceived signal of at least one spreading code interval long, tapcoefficient means for storing the despreading code, fourthmultiplication means for multiplying individual chips stored in thetapped storing means by stored patterns of the despreading code storedin the tap coefficient means, and second addition means for summingoutputs of the fourth multiplication means; and

switching means for supplying the received signal to the initialacquisition means when a phase difference between the received signaland the despreading code is greater than a predetermined value, and forsupplying the received signal to the tracking means when the phasedifference is smaller than the predetermined value.

The synchronizing circuit in accordance with the present invention hasthe initial acquisition circuit for performing correlation detectionusing a matched filter, the sliding correlation detector for performingcorrelation detection, and a switching circuit for selectively supplyingthe received signal to the initial acquisition circuit and thecorrelation detector. The switching circuit supplies the received signalto the initial acquisition circuit during the initial acquisition phase,whereas to the correlation detector once the initial acquisition hasbeen established.

Furthermore, in the correlation detector in accordance with the presentinvention, which holds the synchronism between the received signal andthe replica by using the correlation signal indicating the phasedifference between the spread signal received by the receiver and thereplica of the CDMA spreading code generated by the receiver, thecorrelation signal is compensated for by the tracking means on the basisof the despread signal. This makes it possible for the correlationdetector to achieve accurate tracking.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a synchronizing circuit or an initialacquisition circuit of a conventional matched filter;

FIG. 2 is a block diagram showing a conventional sliding correlator;

FIG. 3 is a block diagram showing a conventional DLL.

FIGS. 4A-4C are diagrams illustrating crosscorrelation output signals interms of a phase error of received signal;

FIG. 5 is a block diagram showing a basic arrangement of a firstembodiment of a correlation detector in accordance with the presentinvention;

FIG. 6 is a block diagram showing another basic arrangement of the firstembodiment of a correlation detector in accordance with the presentinvention;

FIG. 7 is a block diagram showing details of hardware of the correlationdetector in accordance with the present invention; and

FIG. 8 is a block diagram showing another embodiment of a correlationdetector in accordance with the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode for carrying out the invention will now be described withreference to the accompanying drawings.

EMBODIMENT 1

FIG. 5 shows an embodiment of the present invention. A received signal21 applied to the input terminal 10 is selectively supplied through aswitching circuit 42 to an initial acquisition circuit 43 consisting ofa matched filter or to a correlation detector 44. The initialacquisition circuit 43 has an arrangement similar to that of FIG. 1. Thecorrelation detector 44 has a function similar to the correlationdetectors of FIGS. 2 and 3. When the initial acquisition has not yetbeen completed, the received signal is supplied to the initialacquisition circuit (matched filter) 43 in accordance with a switchingsignal 46 from an acquisition decision circuit 45, so that thecorrelation detection is performed. The correlation value detected bythe matched filter 43 is compared with a threshold value in theacquisition decision circuit 45. If the correlation value is greaterthan or equal to the threshold value, the acquisition decision circuit45 decides that the initial acquisition has been completed, and changesthe switching circuit 42 using the switching signal 46. Thus, thereceived signal is inputted to multipliers 47 and 48 in the correlationdetector 44. The acquisition decision circuit 45 provides an initialreset signal 49 to a VCCG 29 and a spreading code replica generator 30.

The received signal 21 after the initial acquisition is multiplied byspreading codes 51 and 52 by the multipliers 47 and 48, the spreadingcodes being generated by the spreading code replica generator 30, andhaving phases shifted forward and backward in time by an amount T (lessthan one chip interval). The two products are passed through bandpassfilters (BPF) 53 and 54, and are square-law detected by square-lawdetectors 55 and 56, in which correlation values are detected. Thecorrelation values are summed in the opposite phase by an adder 57. Thesum is passed through a loop filter 58, and becomes a control voltage ofthe VCCG 29. The clock signal generated by the VCCG 29 regulates thephase of the spreading code replica generator 30, tracks the synchronouspoint, and maintains the synchronization.

FIG. 6 illustrates an example, in which the spreading code replicagenerator 30I is synchronized with the outputs of the quadraturedetector 62 which detects the received signal 21 applied to the inputterminal 10. In this figure, portions corresponding to those of FIG. 5are designated by the same reference numerals. Suffixes I and Q areattached to the same numerals as in FIG. 5 to represent processingcircuits of the two detected outputs I and Q of the quadrature detector62. The detected outputs I and Q are passed through lowpass filters 63and 64, converted into digital signals by A/D converters 65 and 66, andsupplied to switching circuits 42I and 42Q. The outputs of the initialacquisition circuits 43I and 43Q are square-law detected by square-lawdetectors 71 and 72, summed by an adder 73, and supplied to theacquisition decision circuit 45 which decides whether the initialacquisition is established or not.

A spreading code replica generator 30I in the correlation detector 44generates an advanced spreading code 51I with an advanced phase and aretarded spreading code 52I with a retarded phase. Likewise, a spreadingcode replica generator 30Q generates an advanced spreading code 51Q withthe advanced phase and a retarded spreading code 52Q with the retardedphase. The detected output component I outputted from the switchingcircuit 42I is multiplied by the advanced spreading code 51I and theretarded spreading code 52I by multipliers 47I and 48I. Likewise, thedetected output component Q outputted from the switching circuit 42Q ismultiplied by the advanced spreading code 51Q and the retarded spreadingcode 52Q by multipliers 47Q and 48Q.

The detected correlation values with the advanced spreading codes 51Iand 51Q, which are outputted from the multipliers 47I and 47Q, arepassed through bandpass filters (BPFs) 53I and 53Q, square-law detectedby square-law detectors 55I and 55Q, and are summed by an adder 67.Similarly, the detected correlation values with the retarded spreadingcodes 52I and 52Q, which are outputted from the multipliers 48I and 48Q,are passed through bandpass filters (BPFs) 54I and 54Q, square-lawdetected by square-law detectors 56I and 56Q, and are summed by an adder68. The outputs of the adders 67 and 68 are summed in the opposite phaseby the adder 57. These operations are similar to those of FIG. 5.

According to the first embodiment, the synchronization process isseparated into an initial acquisition process, and a tracking processusing the correlation detector. The input PN sequence is acquired sothat the phase difference between the input PN sequence and thereference PN sequence is settled within a range sufficiently smallerthan ± one chip interval during the initial acquisition because theautocorrelation of the PN sequence is established only within a range of± one chip. The tracking processing holds the phase difference betweenthe input PN sequence and the reference PN sequence within the range.

EMBODIMENT 2

FIG. 7 is a block diagram of a correlation detector of a secondembodiment. In FIG. 7, the same functional blocks are designated by thesame reference numerals as in FIGS. 1-6. As shown in FIG. 7, a signalapplied to the input terminal 10 is quasi-coherent detected by adetector 104 using a local signal generated by a local oscillator 103.The local signal has a fixed frequency substantially equal to the centerfrequency of the modulated signal. The correlation detector includesmultipliers 47 and 48 for detecting correlations between the receivedspreading code and replicas of the spreading code; bandpass filters 83and 84 for extracting only correlation detection signals from theproducts; a carrier frequency error compensator 208 for compensating thefiltered output signals with a carrier frequency error signal detectedby an automatic frequency control circuit; an adder 57 for summing inthe opposite phase the correlation detection signal associated with anadvanced phase replica and the correlation detection signal associatedwith a retarded phase replica; a loop filter 58 for averaging the phaseerror of the correlation detection; a multiplier 111 for performingcorrelation detection using a replica in phase with the spreading codeincluded in the received signal; an integral-dump circuit 112 forintegrating the output signal of the multiplier 111 over M chipintervals; an automatic frequency control Circuit 213 for detecting thecarrier frequency error from the output signal of the integral-dumpcircuit to compensate the carrier frequency error; a demodulator 113 formaking decision of the received data after compensating the receivedphase error of the signal obtained by the correlation detection; amultiplier 114 for performing inverse modulation of the decided datausing the phase error signal outputted from the loop filter; a voltagecontrolled clock generator 29 for controlling the clock phase by thephase error signal outputted from the multiplier 114; and the spreadingcode replica generator 30 driven by the clock signal outputted from thevoltage controlled clock generator 29.

The modulated signal, which is down-converted by the fixed oscillationfrequency substantially equal to the center frequency of the modulatedsignal, is deprived of harmonic components, and is multiplied by thereplica of the spreading code in phase with the spreading code in themodulated signal, followed by a predetermined length of time integral.Thus, correlation peaks are detected. The correlation detection signalundergoes decision by the demodulation circuit which performs coherentdetection or delay detection. On the other hand, the modulated signal ismultiplied by the replica of the spreading code with an advanced phase Δwith respect to the spreading code in the modulated signal, and alsomultiplied by the replica of the spreading code with a retarded phase Δ,thereby eliminating the harmonic components.

The error signals between the correlation associated with the advancedphase replica of the spreading code and the correlation associated withthe retarded phase replica of the spreading code are added in theopposite phase by the adder 57, and its output is integrated andaveraged by the loop filter 58. This results in an error voltagecorresponding to the phase error between the spreading code in thereceived signal and the replica of the spreading code. Inversemodulation by multiplying the error voltage by the decided dataoutputted from the demodulator eliminates the error in the phase errorsignal due to the modulated signal. A delay is inserted after the phaseerror detection loop in order to match the absolute times of theprocessings of the phase error detection loop and the data decisionloop.

In the conventional DLL, a despread signal includes, a phase errorsignal component that is a component of an error between the centerfrequency of the received signal and the frequency of the localoscillator of the quadrature detector. The despread signal also includesdata modulation components and vestigial components of a carrier signalcomponent. To eliminate the carrier frequency offset component and thedata modulation components, the despread signal may be squared by asquare-law detector. This, however, will increase noise componentsbecause they are also squared, and the noise components will be added tothe chip phase error, thereby increasing phase jitter.

Accordingly, it is necessary to obviate the square-law detector toprevent the noise component from increasing. In view of this, thepresent embodiment eliminates the carrier frequency offset componentfrom the despread signal by the AFC, and removes the data modulationcomponent by inversely modulating the demodulated and detected signalinto the despread signal.

Since the quasi-coherent detected signal includes a carrier offsetsignal, the detected signal is involved with phase rotations.Consequently, the carrier offset signal must be removed. This isachieved by detecting, by the automatic frequency control circuit 213,the offset component of the carrier signal from the correlation peaks inthe data decision loop, and by correcting the two correlation detectedsignals of the chip phase error detection loop by the carrier offsetsignal in the opposite phase directions.

SUPPLEMENTS

FIG. 8 is a block diagram showing detailed hardware of the correlationdetector described in the second embodiment. In this figure, the sameelements are designated by the same reference numerals as in FIG. 7. InFIG. 8, the reference numerals 304 designates a 90-degree phase shifter,65 and 66 designate A/D converters, 308 and 309 designate complexmultipliers, 313 designates a delay circuit, 314 designates a complexmultiplier, and 317 designates a decision circuit. The reference numeral410 designates a carrier frequency error compensation circuit, and 416designates an automatic frequency control circuit.

In the correlation detector, a received IF modulated signal isquadrature-detected by the quadrature detector. The quadrature-detectedI and Q channel signals are deprived of harmonic components, and areconverted into digital values by the A/D converters 65 and 66, followedby the correlation detection by applying complex signal processings on I(In-phase) and Q (Quadrature) components. The correlation detection iscarried out by complex multiplication of the modulation spread signal bythe I and Q components of the replicas of the spreading code. The tworeplicas of the spreading code is the same if the in-phase andquadrature components of the primary modulated signal are spread by thesame spreading code.

The operation will now be described when the primary modulation is QPSKand the secondary modulation is BPSK. The data to be modulated areprimary modulated independently by binary data which are independentlyset for I and Q channels (QPSK modulation). The I and Q channel data arespread (secondary modulated) by the same spreading codes. The inputsignal to the receiver is expressed by the following equation. ##EQU14##The signals after multiplying the input signal of equation (3) by thereplicas of the spreading code at the receiver will be expressed asfollows if a conventional calculation method is applied. ##EQU15## Thechip phase error signal at the output of the loop filter is expressed bythe following equation.

    e(t)=y.sub.-.sup.2 (t)-y.sub.+.sup.2 (t)=SK.sub.m.sup.2 {m.sub.1.sup.2 (t-τ.sub.t)}+m.sub.2.sup.2 (t-τ.sub.t)D(ε.sub.t)+K.sub.m.sup.2 n.sub.e (t,ε)(18)

As shown by equation (18), since modulated signal powers of individualsymbol components are multiplied by the phase error signal in theprimary QPSK modulation, the primary modulated signal components can beeliminated by inversely modulating the I and Q components of the dataafter decision into the phase error signal.

INDUSTRIAL APPLICABILITY

As described above in detail, according to the present invention, thecorrelation detection during the acquisition phase which requires a highspeed synchronization is carried out in the initial acquisition circuitusing a matched filter, and the correlation detection during thetracking phase which requires power saving rather than high speedsynchronization is performed by the sliding correlation detector. Thismakes it possible to achieve the high speed acquisition, and powersaving during the tracking because the power consumption of the initialacquisition circuit during the tracking is negligible.

In addition, according to the present invention, since the tracking loopof the received chip phase eliminates the primary modulated signalcomponents which are included in the phase error signal of the replicasignals, components only depending on the crosscorrelation can beextracted. This makes high accuracy tracking possible.

What is claimed is:
 1. Synchronizing apparatus including a tracking means for maintaining synchronization between a received signal and a despreading code by using a correlation between the received signal and the despreading code, the received signal being CDMA spread and received by a receiver, and the despreading code being used for despreading the received signal, said tracking means comprising:replica generating means for generating a phase advanced replica of a CDMA spreading code with an advance phase with respect to said received signal, a phase retarded replica of the CDMA spreading code with a retarded phase with respect to said received signal, and a phase synchronized replica of the CDMA spreading code with synchronized phase with respect to said received signal first multiplication means for multiplying said received signal by said phase advanced replica; second multiplication means for multiplying said received signal by said phase retarded replica; a first filter for extracting from an output signal of said first multiplication means a first correlation detection signal indicating a correlation between said phase advanced replica and said received signal; a second filter for extracting from an output signal of said second multiplication means a second correlation detection signal indicating a correlation between said phase retarded replica and said received signal; carrier frequency error compensation means for compensating for a carrier frequency error associated with said first and second correlation detection signals; addition means for summing in opposite phase said first and second correlation detection signals, which have been compensated by said carrier frequency error compensation means; averaging means for averaging an output signal of said addition means along a time axis; third multiplication means for multiplying said received signal by said replica in synchronism with said received signal; integral means for integrating an output signal of said third multiplication means over M chip intervals; automatic frequency control means for detecting said carrier frequency error from an output signal of said integral means, and for compensating for said carrier frequency error; decision means for outputting a decided signal of received data by performing received phase error compensation on the output signal of said integral means; inverse modulation means for inversely modulation an output signal of said averaging means by said decided signal; and clock generating means for outputting a clock signal whose phase is controlled by a phase error signal outputted from said inverse modulation means, wherein said replica generating means generates said replica in accordance with said clock signal generated by said clock generating means.
 2. The synchronizing apparatus as claimed in claim 1, further comprising:initial acquisition means including tapped storing means for storing said received signal of at least one spreading code interval long, tap coefficient means for storing said despreading code, fourth multiplication means for multiplying individual chips stored in said tapped storing means by stored patterns of said despreading code stored in said tap coefficient means, and second addition means for summing outputs of said fourth multiplication means; and switching means for supplying said received signal to said initial acquisition means when a phase difference between said received signal and said despreading code is greater than a predetermined value, and for supplying said received signal to said tracking means when said phase difference is smaller than said predetermined value.
 3. CDMA communication apparatus including a tracking means for maintaining synchronization between a received signal and a despreading code by using a correlation between the received signal and the despreading code, the received signal being CDMA spread and received by a receiver, and the despreading code being used for despreading the received signal, said tracking means comprising:replica generating means for generating a phase advanced replica of a CDMA spreading code with an advanced phase with respect to said received signal, a phase retarded replica of the CDMA spreading code with a retarded phase with respect to said received signal, and a phase synchronized replica of the CDMA spreading code with synchronized phase with respect to said received signal; first multiplication means for multiplying said received signal by said phase advanced replica; second multiplication means for multiplying said received signal by said phase retarded replica; a first filter for extracting from an output signal of said first multiplication means a correlation detection signal indicating a correlation between said phase advanced replica and said received signal; a second filter for extracting from an output signal of said second multiplication means a correlation detection signal indicating a correlation between said phase retarded replica and said received signal; third multiplication means for multiplying said received signal by said replica in synchronism with said received signal; integral means for integrating an output signal of said third multiplication means over M chip intervals; automatic frequency control means for detecting said carrier frequency error from an output signal of said integral means, and for compensating for said carrier frequency error; carrier frequency error compensation means for compensating for a carrier frequency error associated with outputs of said first and second correlation detection signals; addition means for summing in opposite phase said first and second correlation detection signals, which have been compensated by said carrier frequency error compensation means; averaging means for averaging an output signal of said addition means along a time axis; decision means for outputting a decided signal of received data by performing received phase error compensation on the output signal of said integral means; inverse modulation means for inversely modulating an output signal of said averaging means by said decided signal; and clock generating means for outputting a clock signal whose phase is controlled by a phase error signal outputted from said inverse modulation means, wherein said replica generating means generates said replica in accordance with said clock signal generated by said clock generating means.
 4. The CDMA communication apparatus as claimed in claim 3, further comprising:initial acquisition means including tapped storing means for storing said received signal of at least one spreading code interval long, tap coefficient means for storing said despreading code, fourth multiplication means for multiplying individual chips stored in said tapped storing means by stored patterns of said despreading code stored in said tap coefficient means, and second addition means for summing outputs of said fourth multiplication means; and switching means for supplying said received signal to said initial acquisition means when a phase difference between said received signal and said despreading code is greater than a predetermined value, and for supplying said received signal to said tracking means when said phase difference is smaller than said predetermined value.
 5. A synchronizing method including a tracking step of maintaining synchronization between a received signal and a despreading code by using a correlation between the received signal and the despreading code, the received signal being CDMA spread and received by a receiver, and the despreading code being used for despreading the received signal, said tracking step comprising the steps of:generating a phase advanced replica of a CDMA spreading code with an advance phase with respect to said received signal, a phase retarded replica of the CDMA spreading code with a retarded phase with respect to said received signal and a phase synchronized replica of the CDMA spreading code with synchronized phase with respect to said received signal; multiplying said received signal by said phase advanced replica; extracting, from products of the multiplications, correlation detection signals indicating correlations between said replicas and said received signal; compensating for a carrier frequency error associated with said two correlation detection signals; adding in opposite phase said two correlation detection signals whose carrier frequency error is compensated; averaging a summed result along a time axis; multiplying said received signal by said replica in synchronism with said received signal; integrating the product over M chip intervals; detecting said carrier frequency error from the integrated signal, and for compensating for said carrier frequency error; outputting a decided signal of received data by performing received phase error compensation on the integrated signal; inversely modulating the averaged summed result by said decided signal, thereby generating a phase error signal; and generating a clock signal whose phase is controlled by said phase error signal, wherein said replica is generated in accordance with said clock signal.
 6. The synchronizing method as claimed in claim 5, further comprising:an initial acquisition step of storing said despread code, storing said received signal of at least one spreading code interval long, multiplying individual chips of said received signal by individual patterns of said despreading code, and summing the products; and switching step of performing initial acquisition of said received signal in said initial acquisition step when a phase difference between said received signal and said despreading code is greater than a predetermined value, and of tracking said received signal in said tracking step when said phase difference is smaller than said predetermined value.
 7. A CDMA communication system including receivers, each of the receivers being provided with a tracking means for maintaining synchronization between a received signal and a despreading code by suing a correlation between the received signal and the despreading code, the received signal being CDMA spread and received by the receiver, and the despreading code being used for despreading the received signal, said tracking means comprising:replica generating means for generating a phase advanced replica of a CDMA spreading code with an advance phase with respect to said received signal, a phase retarded replica of the CDMA spreading code with a retarded phase with respect to said received signal, and a phase synchronized replica of the CDMA spreading code with synchronized phase with respect to said received signal; first multiplication means for multiplying said received signal by said phase advanced replica; second multiplication means for multiplying said received signal by said phase retarded replica; a first filter for extracting from an output signal of said first multiplication means a correlation detection signal indicating a correlation between said phase advanced replica and said received signal; a second filter for extracting from an output signal of said second multiplication means a correlation detection signal indicating a correlation between said phase retarded replica and said received signal; third multiplication means for multiplying said received signal by said replica in synchronism with said received signal; integral means for integrating an output signal of said third multiplication means over M chip intervals; automatic frequency control means for detecting said carrier frequency error from an output signal of said integral means, and for compensating for said carrier frequency error; carrier frequency error compensation means for compensating for a carrier frequency error associated with said first and second correlation detection signals; addition means for summing in opposite phase said output of said first filter and said output of said second filter, which have been compensated by said carrier frequency error compensation means; averaging means for averaging an output signal of said addition means along a time axis; decision means for outputting a decided signal of received data by performing received phase error compensation on the output signal of said integral means; inverse modulation means for inversely modulation an output signal of said averaging means by said decided signal; and clock generating means for outputting a clock signal whose phase is controlled by a phase error signal outputted from said inverse modulation means, wherein said replica generating means is driven by said clock signal generated by said clock generating means.
 8. The CDMA communication system as claimed in claim 7, further comprising:initial acquisition means including tapped storing means for storing said received signal of at least one spreading code interval long, tap coefficient means for storing said despreading code, fourth multiplication means for multiplying individual chips stored in said tapped storing means by stored patterns of said despreading code stored in said tap coefficient means, and second addition means for summing outputs of said fourth multiplication means; and switching means for supplying said received signal to said initial acquisition means when a phase difference between said received signal and said despreading code is greater than a predetermined value, and for supplying said received signal to said tracking means when said phase difference is smaller than said predetermined value.
 9. A receiver for a CDMA communication system including a plurality of the receivers, each of the receivers being provided with a tracking means for maintaining synchronization between a received signal and a despreading code by suing a correlation between the received signal and the despreading code, the received signal being CDMA spread and received by the receiver, and the despreading code being used for despreading the received signal, said tracking means in the receiver comprising:replica generating means for generating a phase advanced replica of a CDMA spreading code with an advance phase with respect to said received signal, a phase retarded replica of the CDMA spreading code with a retarded phase with respect to said received signal, and a phase synchronized replica of the CDMA spreading code with synchronized phase with respect to said received signal; first multiplication means for multiplying said received signal by said phase advanced replica; second multiplication means for multiplying said received signal by said phase retarded replica; a first filter for extracting from an output signal of said first multiplication means a correlation detection signal indicating a correlation between said phase advanced replica and said received signal; a second filter for extracting from an output signal of said second multiplication means a correlation detection signal indicating a correlation between said phase retarded replica and said received signal; third multiplication means for multiplying said received signal by said replica in synchronism with said received signal; integral means for integrating an output signal of said third multiplication means over M chip intervals; automatic frequency control means for detecting said carrier frequency error from an output signal of said integral means, and for compensating for said carrier frequency error; carrier frequency error compensation means for compensating for a carrier frequency error associated with said first and second correlation detection signals; addition means for summing in opposite phase said output of said first filter and said output of said second filter, which have been compensated by said carrier frequency error compensation means; averaging means for averaging an output signal of said addition means along a time axis; decision means for outputting a decided signal of received data by performing received phase error compensation on the output signal of said integral means; inverse modulation means for inversely modulation an output signal of said averaging means by said decided signal; and clock generating means for outputting a clock signal whose phase is controlled by a phase error signal outputted from said inverse modulation means, wherein said replica generating means is driven by said clock signal generated by said clock generating means. 